The present invention is related to a new type of flash EEPROM wrapper for systems on integrated circuit with embedded flash-EEPROM and CPU.
Integrated systems to interface a flash memory with a CPU are existing. Generally, they combine a direct first Interface with the CPU to access the flash in read operation and a dedicated second interface which support the program/erase functions, either from primary pins of the chip, or from a dedicated programming circuitry.
These existing solutions use two different interfaces for read and program/erase operations, in the case of external interface, some signals needs to be routed to the external world. It is not easy to replace the flash memory by RAM or ROM, both for hardware (modifications in modules, control, . . . ) and software which access the flash memory, especially for program/erase functions.
None of the available prior art flash modules allow a plug-and-play replacement of the flash module by another memory type. Replacement of a flash module usually requires hardware modification to create support for the memory types that will be used in the end product (RAM or ROM in most cases).
The present invention aims to provide a flash memory module, for use in a system on integrated circuit, which can be replaced easily by another memory type such as RAM or ROM.
The present invention concerns a flash EEPROM memory module acting like a synchronous RAM or ROM, for use in an integrated circuit controlled by a CPU, comprising
an asynchronous flash EEPROM memory comprising function control means and operational mode control means for setting the memory""s functional and operational mode state,
an interface for communication with a CPU,
a state machine arranged to control said function control means, and
a plurality of registers arranged to control said operational control means, characterised in that said state machine and said registers are arranged to be directly controlled by standard CPU signals through said interface. Standard CPU signals as they are used for controlling synchronous RAM or ROM comprises chip select, Read/Write, Address and Data signals.
The function set by the function control means can be selected from the group consisting of Read, Program and Erase.
The operational mode set by the operational mode control means can comprise writing mode, write protection mode, and memory address selection.
The flash EEPROM of the present invention can in a preferred embodiment further comprise a timer controlled by the state machine.
The flash EEPROM can also, if necessary, further comprise a second interface arranged for programming said flash EEPROM from outside the integrated circuit, thus from the external world. Another aspect of the present invention is an integrated circuit controlled by a CPU, characterised in that it comprises a flash EEPROM memory module according to the present invention.
It is to be noticed that the term xe2x80x98comprisingxe2x80x99, used in the claims, should not be interpreted as being limitative to the means listed thereafter. Thus, the scope of the expression xe2x80x98a device comprising means A and Bxe2x80x99 should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.